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1 * this specification are subject to be changed without notice. EM78056 8-bit micro-controller for general purpose product 8.21.1996 general description the EM78056 is an 8-bit microprocessor with low-power, high speed cmos technology. integrated onto a single chip are on-chip watchdog timer (wdt), ram, rom, programmable real time clock/counter, power down mode, and tri-state i/o. features ? operating voltage range : 2.5v ~ 5.5v ? available in temperature range: 0 c ~ 70 c. ? optional instruction cycle period : two oscillator clocks, or four oscillator clocks ? operating frequency range two oscillator clocks per instruction cycle : crystal type : dc~12mhz at 5v dc~4mhz at 3v rc type : dc~4mhz at 5v dc~4mhz at 3v four oscillator clocks per instruction cycle : crystal type : dc~24mhz at 5v dc~6mhz at 3v rc type : dc~4mhz at 5v dc~4mhz at 3v ? 1k x 13 on chip rom. ? 9 special function registers. ? 33 x 8 general purpose register (sram). ? two bi-directional tri-state i/o ports (12 i/o pins). ? 2 level stack for subroutine nesting. ? 8-bit real time clock/counter (tcc) with selective signal sources and trigger edges. ? programmable free running on-chip watchdog timer. ? two r-option pins. ? selectable oscillator options: xtal1 type (high frequency), xtal2 type (32.768 khz), external clock input, rc type. ? 99.9% single instruction cycle commands. ? 18 pin dip, 18 pin soic, 20 pin ssop. EM78056 pin assignments patent number : 62706, 61007 (r.o.c) patent pending : 83216083 (r.o.c) 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 EM78056p p52 p53 tcc reset v ss v ss p60 p61 p62 p63 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 p51 p50 osci osco v dd v dd p67 p66 p65 p64 EM78056s ssop 20 pin dip 18 pin p52 p53 tcc reset v ss p60 p61 p62 p63 p51 p50 osci osco v dd p67 p66 p65 p64 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 EM78056m soic 18 pin p52 p53 tcc reset v ss p60 p61 p62 p63 p51 p50 osci osco v dd p67 p66 p65 p64 8-bit micro-controller for general purpose product
* this specification are subject to be changed without notice. EM78056 8-bit micro-controller for general purpose product 2 8.21.1996 functional block diagram fig. 2 functional block diagram pin descriptions symbol i/o function osci i xtal type : crystal input terminal or external clock input pin. rc type: rc oscillator input pin. osco i/o xtal type: output terminal for crystal oscillator or external clock input pin. rc type: clock output with a period of one instruction cycle is put on this pin. tcc i real time clock/counter, schmitt trigger input pin. must be tied to v dd or v ss if not in use. reset i schmitt trigger input pin. if this pin remains logic low, the controller is reset. p50~p53 i/o p50~p53 are bi-directional i/o ports. p50 and p51 are also the r-option pins. p60~p67 i/o p60~p67 are bi-directional i/o ports. v dd - power supply pin. v ss - ground pin.
3 * this specification are subject to be changed without notice. EM78056 8-bit micro-controller for general purpose product 8.21.1996 function descriptions operational registers r0 (indirect addressing register) ? r0 is not a physically implemented register. it is useful as indirect addressing pointer. any instruction using r0 as register actually accesses data pointed by the ram select register (r4). r1 (tcc) ? increased by an external signal edge applied to tcc pin, or by the instruction cycle clock. ? written and read by the program as any other register. r2 (program counter) & stack ? r2 and hardware stack are 10-bit wide. the structure is depicted in fig.3. ? generates 1k x 13 on-chip rom addresses to the relative programming instruction codes. one program page is 512 words long. ? r2 is set all "1"s upon a reset condition. ? "jmp" instruction allows the direct loading of the lower 9 program counter bits. thus, jmp allows jmup to any loaction on one page. ? call instruction loads the lower 9 bits of the pc, and then pc+1 is pushed into the stack. thus, the subroutine entry address can be any loaction on one page. ? ret (retl k,reti) instruction loads the program counter with the contents at the top of stack. ? mov r2,a allows the loading of an address from the a register to the lower 8-bits of pc, and the ninth bit (a8) of pc is cleared. ? add r2,a allows a relative address be added to the current pc, and the ninth bit of pc is cleared. ? any instruction which writes to r2 (e.g. add r2,a,mov r2,a,bc r2,6, ...)(except tbl) will cause the ninth bit (a8) of pc to be cleared. thus, the computed jump is limited to the first 256 locations of any program page. ? tbl allows a relative address be added to the current pc (r2+a ? r2), and content of the ninth bit (a8) of pc is not changed. thus, the computed jump can be on the second 256 locations on one program page. ? the most significant bit (a9) will be loaded with the content of bit ps in the status register (r3) upon the execution of a jmp, call, or any instruction which writes to r2. ? all instructions are single instruction cycle (fclk/2) except that the instructions which write to r2 need one more instruction cycle. r3 (status register) 76543210 gp1 gp0 ps t p z dc c bit 0 (c) carry flag bit 1 (dc) auxiliary carry flag bit 2 (z) zero flag. set to 1 if the result of an arithmetic or logic operation is zero. bit 3 (p) power down bit. set to 1 during power on or by a wdtc command and reset to 0 by a slep command. bit 4 (t) time-out bit. set to 1 by the slep and wdtc command, or during power up and reset to 0 by wdt timeout.
* this specification are subject to be changed without notice. EM78056 8-bit micro-controller for general purpose product 4 8.21.1996 bit 5 (ps) page select bit. 0 : page 0 (address: 000~1ff) 1 : page 1 (address: 200~3ff) ps is used to preselect a program memory page. when executing a jmp, call, or other instruction causes program counter to be changed (e.g. mov r2,a), ps is loaded into the tenth bit of the program counter, selecting one of the available program memory pages. note that ret (retl, reti) instrunction does not change the ps bit. that is, the return will be always to the page from where the subroutine was called, regardless of the current setting of ps bit. bits 6~7 general purpose read/write bits. r4 (ram select register) bits 0 ~ 5 are used to select up to 40 registers (address: 00~27) in the indirect addressing mode. refer to register r0. bits 6 ~ 7 are not used. (read as 1) if no indirect addressing is used, the rsr can be used as a 6-bit wide general purpose read/write register. see the configuration of the data memory in fig. 4. fig. 4 data memory configuration fig. 3 program counter organization cont stack1 stack2
5 * this specification are subject to be changed without notice. EM78056 8-bit micro-controller for general purpose product 8.21.1996 r5 ~ r6 (port 5 ~ port 6) r5 and r6 are i/o registers. only low order 4 bits are used in r5. the high order 4 bits of r5 will be read as "0". r7 ~ r27 (general purpose register) r7 ~ r27 are the 33 8 general purpose registers. special purpose registers a (accumulator) internal data transfer, or instruction operand holding. its not an addressable register. cont (control register) 76 543 210 - - ts te pab psr2 psr1 psr0 bit 0 (psr0) ~ bit 2 (psr2) tcc/wdt prescaler bits. psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 bit 3 (pab) prescaler assignment bit. 0: tcc 1: wdt bit 4 (te) tcc signal edge. 0: increment from low to high transition on tcc pin 1: increment from high to low transition on tcc pin bit 5 (ts) tcc signal source 0: internal instruction cycle clock 1: transition on tcc pin bits 6~7 not used. cont register is readable and writable. ioc5 ~ ioc6 (i/o port control register) 1 put the relative i/o pin into high impedance, while 0 put the relative i/o pin as output. only low order 4 bits are used in ioc5.
* this specification are subject to be changed without notice. EM78056 8-bit micro-controller for general purpose product 6 8.21.1996 ioc5 and ioc6 registers are readable and writable. ioce (wdt control register) 76 54 3 210 wte - - roc - - - - bit 7 (wte) control bit used to enable watchdog timer. wte bit is used only if the code option bit wtc is "1". if wtc bit is "1", then wdt is disabled/enabled by wte bit. 0: disable wdt 1: enable wdt wte bit is not used if the code option bit wtc is "0". that is, if wtc bit is "0", wdt is always disabled no matter what the wte bit is. wte bit is readable and writable. bit 4 (roc) roc is used for the r-option. setting roc to 1 will enable the status of r-option pins (p50~p51) to be read by the controller. clearing roc will disable the r-option function. if the r-option function is used, the user must connect the p51 pin or/and p50 pin to vss by a 430k w external resistor (rex). if rex is connected/disconnected, the status of p50(p51) will be read as 0/1 when roc is set to 1. refer to fig. 8. roc bit is readable and writable. bits 0 ~ 3, 5~6 not used. tcc/wdt & prescaler there is an 8-bit counter available as prescaler for the tcc or wdt. the prescaler is available for the tcc only or wdt only at the same time and the pab bit of cont register is used to determine the prescaler assignment. the psr0~psr2 bits determine the prescale ratio. the prescaler will be cleared by instructions which write to tcc each time, when assigned to tcc mode. the wdt and prescaler, when assigned to wdt mode, will be cleared by the wdtc and slep instructions. fig. 5 depicts the circuit diagram of tcc/wdt. r1(tcc) is an 8-bit timer/counter. the clock source of tcc can be internal clock external clock input (edge selectable from tcc pin). if tcc signal source is from internal clock, tcc will increase by 1 in every instruction cycle (without prescaler). refer to fig. 5, clk=fosc/2 or clk=fosc/4 is depended on the code option bit clks. clk=fosc/2 if clks bit is "0", and clk=fosc/4 if clks bit is "1". if tcc signal source is from external clock input, tcc will increase by 1 on every falling edge or rising edge of tcc pin. the watchdog timer is a free running on-chip rc oscillator. the wdt will keep running even the oscillator driver has been turned off (i.e. in sleep mode). during the normal operation or the sleep mode, a wdt time- out (if enabled) will cause the device to reset. the wdt can be enabled or disabled at any time during the normal mode by software programming. refer to wte bit of ioce register. with no presacler, the wdt time-out period is approximately 18 ms.
7 * this specification are subject to be changed without notice. EM78056 8-bit micro-controller for general purpose product 8.21.1996 fig. 5 block diagram of tcc and wdt wte clk (fosc/2 or fosc/4) fig. 7 the circuit of i/o port (p50,p51) with r-option fig. 6 the circuit of i/o port and i/o control register
* this specification are subject to be changed without notice. EM78056 8-bit micro-controller for general purpose product 8 8.21.1996 i/o ports the i/o registers, port 5 ~ port 6, are bi-directional tri-state i/o ports. each i/o pin can be defined as input or output pin by the i/o control register (ioc5 ~ ioc6) under program control. p50~p51 are also the r-option pins which are enabled by software. while r-option function is used, p50~p51 are recommended to be used as output pins. during the period of r-option being enabled, p50~p51 must be programmed as input pins. if external resistor is connected to p50(p51) for r-option function, the current consumption should be noticed in the applications that low power are concerned. the i/o registers and i/o control registers are both readable and writable. the i/o interface circuit is shown in fig. 6. reset and wake-up the reset can be caused by fig. 8 block diagram of reset of controller (1) power on reset (2) /reset pin input low, or (3) wdt timeout (if enabled). the device will be kept in a reset condition for a period of approx. 18ms (one oscillator start-up timer period) after the reset is detected. once the reset occurs, the following functions are performed. the oscillator is running, or will be started. the program counter (r2) is set to all 1. the upper 3 bits of r3 are cleared. all i/o port pins are configured as input mode (high-impedance state). the watchdog timer and prescaler are cleared. bits 0~5 of cont register are set to "1". bit 7 of ioce register is set to 1 and bit 4 of ioce is cleared. the sleep mose (power down mode) can be entered by executing the slep instruction. while entering sleep mode, the wdt (if enabled) is cleared but keeping running. the controller can be awakened by (1) external reset input on /reset pin, or (2) wdt time-out (if enabled). the two cases will cause the controller reset. the t and p flags of r3 can be used to determine the source of the reset (wake-up). wte
9 * this specification are subject to be changed without notice. EM78056 8-bit micro-controller for general purpose product 8.21.1996 instruction set each instruction in the instruction set is a 13-bit word divided into an op code and one or more operands. normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction execution mov r2,a, tbl, add r2,a, or instructions of arithmetic or logic operation on r2 (e.g. bs (bc) r2,b, clr r2,.... ). in this case, the execution takes two instruction cycles. under some condition, if the specification of the instruction cycle is not suitable for some applications, they can be modified as follows: (a) one instruction cycle consists of 4 oscillator periods. (b) jmp, call, ret, retl, reti, or the conditional skip (jbs, jbc, jz, jza, djz, djza) is tesed to be true are executed within two instruction cycles. the instructions that write to the program counter also take two instruction cycles. the case(a) is selected by the code option bit (clks). one instruction cycle consists of two oscillator clocks if clks bit is low, or consists of four oscillator clocks if clks bit is high. the case(b) is selected by the code option bit (cyes). the execution of those instructions listed in case (b) takes one instruction cycle if cyes bit is low, or takes two instruction cycles if cyes bit is high. case(a) and case(b) are independent options, that is, they can be selected individually. note that once 4 oscillator periods within one instruction cycle is selected in case(a), the internal clock source to tcc is clk=fosc/4 instead of fosc/ 2 that is shown in fig. 5. in addition, the instruction set has the following features: (1) every bit of any register can be set, cleared, or tested directly. (2) the i/o register can be regarded as general register. that is, the same instruction can operates on i/o register. the symbol r represents a register designator which specifies which one of the registers (including opera- tional registers and general purpose registers) is to be utilized by the instruction. b represents a bit field designator which selects the number of the bit, located in the register r, affected by the operation. k represents an 8 or 9-bit constant or literal value. instruction status binary hex hnemonic operation affected 0 0000 0000 0000 0000 nop no operation none 0 0000 0000 0001 0001 daa decimal adjust a c 0 0000 0000 0010 0002 contw a ? cont none 0 0000 0000 0011 0003 slep 0 ? wdt, stop oscillator t,p 0 0000 0000 0100 0004 wdtc 0 ? wdt t,p 0 0000 0000 rrrr 000r iow r a ? iocr none 0 0000 0001 0010 0012 ret [top of stack] ? pc none 0 0000 0001 0100 0014 contr cont ? a none 0 0000 0001 rrrr 001r ior r iocr ? a none 0 0000 0010 0000 0020 tbl r2+a ? r2, bits 8~9 of r2 unchanged z,c,dc 0 0000 01rr rrrr 00rr mov r,a a ? r none 0 0000 1000 0000 0080 clra 0 ? az 0 0000 11rr rrrr 00rr clr r 0 ? rz 0 0001 00rr rrrr 01rr sub a,r r-a ? a z,c,dc 0 0001 01rr rrrr 01rr sub r,a r-a ? r z,c,dc 0 0001 10rr rrrr 01rr deca r r-1 ? az 0 0001 11rr rrrr 01rr dec r r-1 ? rz
* this specification are subject to be changed without notice. EM78056 8-bit micro-controller for general purpose product 10 8.21.1996 this instruction can operate on ioc5~ioc6, ioce only. instruction status binary hex hnemonic operation affected 0 0010 00rr rrrr 02rr or a,r a r ? az 0 0010 01rr rrrr 02rr or r,a a r ? rz 0 0010 10rr rrrr 02rr and a,r a & r ? az 0 0010 11rr rrrr 02rr and r,a a & r ? rz 0 0011 00rr rrrr 03rr xor a,r a ? r ? az 0 0011 01rr rrrr 03rr xor r,a a ? r ? rz 0 0011 10rr rrrr 03rr add a,r a + r ? a z,c,dc 0 0011 11rr rrrr 03rr add r,a a + r ? r z,c,dc 0 0100 00rr rrrr 04rr mov a,r r ? az 0 0100 01rr rrrr 04rr mov r,r r ? rz 0 0100 10rr rrrr 04rr coma r /r ? az 0 0100 11rr rrrr 04rr com r /r ? rz 0 0101 00rr rrrr 05rr inca r r+1 ? az 0 0101 01rr rrrr 05rr inc r r+1 ? rz 0 0101 10rr rrrr 05rr djza r r-1 ? a, skip if zero none 0 0101 11rr rrrr 05rr djz r r-1 ? r, skip if zero none 0 0110 00rr rrrr 06rr rrca r r(n) ? a(n-1), r(0) ? c, c ? a(7) c 0 0110 01rr rrrr 06rr rrc r r(n) ? r(n-1), r(0) ? c, c ? r(7) c 0 0110 10rr rrrr 06rr rlca r r(n) ? a(n+1), r(7) ? c, c ? a(0) c 0 0110 11rr rrrr 06rr rlc r r(n) ? r(n+1), r(7) ? c, c ? r(0) c 0 0111 00rr rrrr 07rr swapa r r(0-3) ? a(4-7), r(4-7) ? a(0-3) none 0 0111 01rr rrrr 07rr swap r r(0-3) ? r(4-7) none 0 0111 10rr rrrr 07rr jza r r+1 ? a, skip if zero none 0 0111 11rr rrrr 07rr jz r r+1 ? r, skip if zero none 0 100b bbrr rrrr 0xxx bc r,b 0 ? r(b) none 0 101b bbrr rrrr 0xxx bs r,b 1 ? r(b) none 0 110b bbrr rrrr 0xxx jbc r,b if r(b)=0, skip none 0 111b bbrr rrrr 0xxx jbs r,b if r(b)=1, skip none 1 000k kkkk kkkk 1kkk call k pc+1 ? [sp],(page, k) ? pc none 1 010k kkkk kkkk 1kkk jmp k (page, k) ? pc none 1 1000 kkkk kkkk 18kk mov a,k k ? a none 1 1001 kkkk kkkk 19kk or a,k a k ? az 1 1010 kkkk kkkk 1akk and a,k a & k ? az 1 1011 kkkk kkkk 1bkk xor a,k a ? k ? az 1 1100 kkkk kkkk 1ckk retl k k ? a, [top of stack] ? pc none 1 1101 kkkk kkkk 1dkk sub a,k k-a ? a z,c,dc 1 1111 kkkk kkkk 1fkk add a,k k+a ? a z,c,dc
11 * this specification are subject to be changed without notice. EM78056 8-bit micro-controller for general purpose product 8.21.1996 code option register the EM78056 has one code option register which is not part of the normal program memory. the option bits cannot be accessed during normal program execution. 7654 3 21 0 - - lvdd wtc hlf ms clks cyes bit 0 (cyes): instruction cycle option for special instruction. 0: one cycle 1: two cylcles refer to section on instruction set. bit 1 (clks): instruction period option. 0: two oscillator periods 1: four oscillator periods refer to section on instruction set. bit 2 (ms): oscillator type selection. 0: rc type 1: xtal type (xtal1 and xtal2) bit 3 (hlf): xtal frequency selection. 0: xtal2 type (low frequency, 32.768khz) 1: xtal1 type (high frequency) this bit is useful only when bit 2 (ms) is 1. when ms is 0, hlf must be 0. bit 4(wtc): wdt option. 0: wdt is enable. control bit wte in ioce is unused. 1: wdt is enabled. wdt can be disabled/enabled by software programming. control bit wte in ioce is used to disable/enable wdt. bit 5(lvdd): low power control. 0: lvdd must be"0" on the application that vdd>4.5v, and there are appoximately 60 m a dc current. 1: lvdd can be "1" only on the application that vdd<4v, and it can save approximately 15 m a dc current. bit 6: not used, must be 1. bit 7: not used, must be 0.
* this specification are subject to be changed without notice. EM78056 8-bit micro-controller for general purpose product 12 8.21.1996 absolute maximum ratings items sym. condition rating temperature under bias t opr 0 c to 70 c storage temperature t str -65 c to 150 c input voltage v in -0.3v to +6.0v output voltage v o -0.3v to +6.0v ac electrical characteristics (t a =0 c ~ 70 c, v dd =5.0v, v ss =0v) input clk duty cycle dclk 45 50 55 % instruction cycle time tins xtal type 167 dc ns (clks="0") rc type 500 dc ns tcc input period ttcc note 1 (tins+20)/n ns device reset hold time tdrh ta = 25 c18ms watchdog timer period twdt ta = 25 c18ms note 1: n= selected prescaler ratio. parameter symbol condition min. typ. max. unit dc electrical characteristic (t a =0 c ~ 70 c, v dd =5.0v, v ss =0v) parameter sym. condition min. typ. max. unit input leakage current i il v in = v dd , v ss 1 m a for input pins input high voltage v ih 2.0 v input low voltage v il 0.8 v input high threshold voltage v iht reset, tcc 2.0 v input low threshold voltage v ilt reset, tcc 0.8 v clock input high voltage v ihx osci 3.5 v clock input low voltage v ilx osci 1.5 v output high voltage v oh i oh = -12.0ma 2.4 v (port 5,6) output low voltage v ol i ol = 12.0ma 0.4 v (port 5,6) power down current i sb all input and i/o pins at v dd , output 10 m a pin floating, wdt enabled operating supply current i cc1 reset='high', fosc=12mhz (ms=1, clks=0, hlf=1), output pin floating 4 ma operating supply current i cc2 reset='high', fosc=4mhz (ms=1, clks=0, hlf=1), output pin floating 2 ma operating supply current i cc3 reset='high', fosc=32khz (vdd=3v) (ms=1, clks=0, hlf=0), output pin floating, wdt disabled 15 30 m a
13 * this specification are subject to be changed without notice. EM78056 8-bit micro-controller for general purpose product 8.21.1996 (clks="0") (clks="0")

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